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| ht46r24/ht46c24 a/d type 8-bit mcu i 2 c is a trademark of philips semiconductors. rev. 2.00 1 march 2, 2006 general description the ht46r24/ht46c24 are 8-bit, high performance, risc architecture microcontroller devices specifically designed for a/d applications that interface directly to analog signals, such as those from sensors. the mask version ht46c24 is fully pin and functionally compatible with the otp version ht46r24 device. the advantages of low power consumption, i/o flexibil- ity, programmable frequency divider, timer functions, oscillator options, multi-channel a/d converter, pulse width modulation function, i 2 c interface, halt and wake-up functions, enhance the versatility of these de - vices to suit a wide range of a/d application possibilities such as sensor signal processing, motor driving, indus - trial control, consumer products, subsystem controllers, etc. features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v 40 bidirectional i/o lines (max.) 1 interrupt input shared with an i/o line two 16-bit programmable timer/event counter with overflow interrupt on-chip crystal and rc oscillator watchdog timer 8192 16 program memory 384 8 data memory ram supports pfd for sound generation halt function and wake-up feature reduce power consumption up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v 16-level subroutine nesting 8 channels 10-bit resolution a/d converter 4-channel 8-bit pwm output shared with four i/o lines bit manipulation instruction 16-bit table read instruction 63 powerful instructions all instructions in one or two machine cycles low voltage reset function i 2 c bus (slave mode) 28-pin skdip/sop, 48-pin ssop package technical document tools information faqs application note ha0004e ht48 & ht46 mcu uart software implementation method ha0005e controlling the i2c bus with the ht48 & ht46 mcu series ha0013e ht48 & ht46 lcm interface design ha0047e an pwm application example using the ht46 series of mcus
block diagram pin assignment ht46r24/ht46c24 rev. 2.00 2 march 2, 2006 ! " # $ % " & " ' ( ) ( * + * $ , ' - $ , . + $ , ' - + ' ( + / 0 ' ( 0 - / 1 2 2 2 + ' + / 2 1 ' 1 ( 3 4 # . ' ) 5 * * + / 0 ' * - 6 ' 7 ' 1 ' " ) 2 . 5 ) ! + / 1 2 6 ) * * + / * 1 ) ) ) 2 ) + + - 3 - 1 - 7 - 6 - - - 0 - - - + 0 8 0 3 0 1 0 7 0 6 0 - 0 0 0 0 0 + 8 3 1 7 6 0 - 6 7 1 3 8 + 0 - 6 7 1 3 8 + 0 - 2 6 ' 6 2 - ' - 0 ' * + 2 0 ' 0 2 ' 2 ' 2 + ' + * 0 * * 1 7 6 - * + + + 2 7 ' 7 2 1 ' 1 - 6 ' 7 ' 1 ' " * - * 6 * 7 * 1 0 ' ( 0 ' ( ' ( + ' ( + 1 7 6 - 0 3 1 7 6 - 0 + 8 3 1 7 6 0 - 6 7 1 3 8 + 0 - 2 6 ' 6 2 - ' - 0 ' * + 2 0 ' 0 2 ' 2 ' 2 + ' + + 2 7 ' 7 2 1 ' 1 - 6 ' 7 ' 1 ' " ' ( ' + ' ( + - 0 pin description pin name i/o options description pa0~pa2 pa3/pfd pa4 pa5/int pa6/sda pa7/scl i/o pull-high wake-up pa3 or pfd i/o or serial bus bidirectional 8-bit input/output port. each bit can be configured as wake-up input by option (bit option). software instructions determine the cmos out - put or schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). the pfd and int are pin-shared with pa3 and pa5, respectively. once the i 2 c bus function is used, the internal reg - isters related to pa6 and pa7 cannot be used. pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/an6 pb7/an7 i/o pull-high bidirectional 8-bits input/output port. software instructions determine the cmos output, schmitt trigger input with or without pull-high resistor (deter - mined by pull-high option: bit option) or a/d input. once a pb line is se - lected as an a/d input (by using software control), the i/o function and pull-high resistor are automatically disabled. pc0~pc4 (28-pin package only) i/o pull-high bidirectional 8-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without pull-high resistor (deter - mine by pull-high option: byte option). pc0~pc7 (48-pin package only) pd0/pwm0 pd1/pwm1/tmr1 (28-pin package only) i/o pull-high pwm bidirectional 8-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without a pull-high resistor. the pwm0 output function is pin-shared with pd0. the pwm1 output function is pin-shared with pd1 and tmr1. (determined by pull-high option: byte option) pd0/pwm0 pd1/pwm1 pd2/pwm2 pd3/pwm3 pd4~pd7 (48-pin package only) i/o pull-high pwm bidirectional 8-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without a pull-high resistor (de- termined by pull-high option: byte option). the pwm0/pwm1/pwm2/ pwm3 output function are pin-shared with pd0/pd1/pd2/pd3 (depending on the pwm options). pf0~pf7 (48-pin package only) i/o pull-high bidirectional 8-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without pull-high resistor (deter- mine by pull-high option: byte option). tmr0 i timer/event counter 0 schmitt trigger input (without pull-high resistor) tmr1 (48-pin package only) i timer/event counter 1 schmitt trigger input (without pull-high resistor). res i schmitt trigger reset input, active low vss negative power supply, ground vdd positive power supply osc1 osc2 i o crystal or rc osc1 and osc2 are connected to an rc network or a crystal (by options) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. test1~3 i test mode input pin it disconnects in normal operation. nc no connection ht46r24/ht46c24 rev. 2.00 3 march 2, 2006 absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v i dd1 operating current (crystal osc) 3v no load, f sys =4mhz adc disable 0.6 1.5 ma 5v 24ma i dd2 operating current (rc osc) 3v no load, f sys =4mhz adc disable 0.8 1.5 ma 5v 2.5 4 ma i dd3 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz adc disable 48ma i stb1 standby current (wdt enabled) 3v no load, system halt 5 a 5v 10 a i stb2 standby current (wdt disabled) 3v no load, system halt 1 a 5v 2 a v il1 input low voltage for i/o ports, tmr0, tmr1 and int 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr0, tmr1 and int 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset voltage 2.7 3 3.3 v i ol i/o port sink current 3v v ol =0.1v dd 48 ma 5v 10 20 ma i oh i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 10 ma r ph pull-high resistance 3v 20 60 100 k 5v 10 30 50 k v ad a/d input voltage 0 v dd v e ad a/d conversion error 0.5 1 lsb i adc additional power consumption if a/d converter is used 3v 0.5 1 ma 5v 1.5 3 ma ht46r24/ht46c24 rev. 2.00 4 march 2, 2006 a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f timer timer i/p frequency (tmr0/tmr1) 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 *t sys t int interrupt pulse width 1 s t ad a/d clock period 1 s t adc a/d conversion time 76 t ad t adcs a/d sampling time 32 t ad t iic i 2 c bus clock period connect to external pull-high resistor 2k 64 *t sys note: *t sys =1/f sys ht46r24/ht46c24 rev. 2.00 5 march 2, 2006 ht46r24/ht46c24 rev. 2.00 6 march 2, 2006 functional description execution flow the system clock is derived from either a crystal or an rc oscillator. it is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and ex - ecution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. the pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. if an instruction changes the value of the program counter, two cycles are required to com - plete the instruction. program counter pc the program counter (pc) is 13 bits wide and it controls the sequence in which the instructions stored in the pro - gram rom are executed. the contents of the pc can specify a maximum of 8192 addresses. after accessing a program memory word to fetch an instruction code, the value of the pc is incremented by 1. the pc then points to the memory word containing the next instruc - tion code. when executing a jump instruction, condi - tional skip execution, loading a pcl register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the pc manipulates the program transfer by loading the ad - dress corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; oth - erwise proceed to the next instruction. the lower byte of the pc (pcl) is a readable and writeable register (06h). moving data into the pcl per - forms a short jump. the destination is within 256 loca - tions. when a control transfer takes place, an additional dummy cycle is required. 0 - 0 - 0 - * # ) ) 9 : ; ) ) 9 4 : * # ) ) 9 < : ; ) ) 9 : * # ) ) 9 < : ; ) ) 9 < : < < ) . = ) 9 ) . : execution flow mode program counter *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000000 external interrupt 0000000000100 timer/event counter 0 overflow 0000000001000 timer/event counter 1 overflow 0000000001100 a/d converter interrupt 0000000010000 i 2 c bus interrupt 0000000010100 skip program counter + 2 loading pcl *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *12~*0: program counter bits s12~s0: stack register bits #12~#0: instruction code bits @7~@0: pcl bits ht46r24/ht46c24 rev. 2.00 7 march 2, 2006 program memory eprom the program memory (eprom) is used to store the pro - gram instructions which are to be executed. it also con - tains data, table, and interrupt entries, and is organized into 8192 16 bits which are addressed by the program counter and table pointer. certain locations in the rom are reserved for special usage: location 000h location 000h is reserved for program initialization. after chip reset, the program always begins execution at this location. location 004h location 004h is reserved for the external interrupt service program. if the int input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004h. location 008h location 008h is reserved for the timer/event coun - ter 0 interrupt service program. if a timer interrupt re - sults from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the pro - gram begins execution at location 008h. location 00ch location 00ch is reserved for the timer/event coun - ter 1 interrupt service program. if a timer interrupt re - sults from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the pro - gram begins execution at location 00ch. location 010h location 010h is reserved for the a/d converter inter - rupt service program. if an a/d converter interrupt re - sults from an end of a/d conversion, and if the interrupt is enabled and the stack is not full, the pro - gram begins execution at location 010h. location 014h this area is reserved for the i 2 c bus interrupt service program. if the i 2 c bus interrupt resulting from a slave address is match or completed one byte of data trans - fer, and if the interrupt is enable and the stack is not full, the program begins execution at location 014h. table location any location in the rom can be used as a look-up ta - ble. the instructions tabrdc [m] (the current page, page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to tblh (table higher-order byte register) (08h). only the destination of the lower-order byte in the table is well-defined; the other bits of the ta - ble word are all transferred to the lower portion of tblh. the tblh is read only, and the table pointer (tblp) is a read/write register (07h), indicating the ta- ble location. before accessing the table, the location should be placed in tblp. all the table related instruc- tions require 2 cycles to complete the operation. these areas may function as a normal rom depend- ing upon the users requirements stack register stack this is a special part of the memory which is used to save the contents of the program counter (pc) only. the stack is organized into 16 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at the state of a subroutine call or an interrupt acknowl - edgment, the contents of the program counter are pushed onto the stack. at the end of the subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the program counter is restored to its previous 5 ) . > ) ; . ) ) ? ' 5 ) ) + ) ) ? " = 4 ) ? . ) 9 6 7 ) @ ! : " = 4 ) ? . ) 9 6 7 ) @ ! : a ) ) ) $ ) + ) ) * ' ) 5 ) ) 2 ) * * * & * * & ' 5 ) ) ) ) ? * + + & 7 ) ? + + + & + + - & + + 3 & + + & + + & + - & + + & program memory instruction table location *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 11111@7@6@5@4@3@2@1@0 table location note: *12~*0: table location bits p12~p8: current program counter bits @7~@0: table pointer bits ht46r24/ht46c24 rev. 2.00 8 march 2, 2006 value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt is serviced. this feature prevents stack overflow, allowing the programmer to use the structure more easily. if the stack is full and a call is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 16 return addresses are stored). data memory ram the data memory (ram) is designed with 424 8 bits, and is divided into two functional groups, namely; spe - cial function registers (40 8 bits) and general purpose data memory (bank 0:192 8 bits and bank 1:192 8 bits) most of which are readable/writeable, although some are read only. the special function registers are overlapped in any banks. of the two types of functional groups, the special function registers consist of an indirect addressing reg - ister 0 (00h), a memory pointer register 0 (mp0;01h), an indirect addressing register 1 (02h), a memory pointer register 1 (mp1;03h), a bank pointer (bp;04h), an accumulator (acc;05h), a program counter lower-order byte register (pcl;06h), a table pointer (tblp;07h), a table higher-order byte register (tblh;08h), a status register (status;0ah), an inter- rupt control register 0 (intc0;0bh), a timer/event counter 0 (tmr0h:0ch; tmr0l:0dh), a timer/event counter 0 control register (tmr0c;0eh), a timer/event counter 1 (tmr1h:0fh; tmr1l:10h), a timer/event counter 1 control register (tmr1c; 11h), interrupt con- trol register 1 (intc1;1eh), pwm data register (pwm0;1ah, pwm1;1bh, pwm2;1ch, pwm3;1dh), the i 2 c bus slave address register (hadr;20h), the i 2 c bus control register (hcr;21h), the i 2 c bus status reg - ister (hsr;22h), the i 2 c bus data register (hdr;23h),the a/d result lower-order byte register (adrl;24h), the a/d result higher-order byte register (adrh;25h), the a/d control register (adcr;26h), the a/d clock setting register (acsr;27h), i/o registers (pa;12h, pb;14h, pc;16h, pd;18h, pf; 28h) and i/o control registers (pac;13h, pbc;15h, pcc;17h, pdc;19h, pfc;29h). the remaining space before the 40h is reserved for future expanded usage and reading these locations will get 00h . the space before 40h is overlapping in each bank. the general purpose data memory, addressed from 40h to ffh (bank0; bp=0 or bank1; bp=1), is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0;01h/mp1;03h). the space before 40h is overlapping in each bank. after first setting up bp to the value of 01h to access bank 1, this bank must then be accessed indirectly using the memory pointer mp1. with bp set to a value of 01h , using mp1 to indirectly read or write to the data memory areas with addresses from 40h~ffh will result in operations to bank 1. directly addressing the data ! " ! " # $ % & ' & ( ( ) % * % + # % + , % + - " " . % & & & % / ' / . % & & & % / ' / 0 1 0 1 0 1 1 $ . 2 1 1 ' 1 ' 0 1 ' 1 ' 1 ' 0 1 ' 3 3 3 3 . 2 1 ' ' ' ' ' 0 ' ' ' " " " ram mapping ht46r24/ht46c24 rev. 2.00 9 march 2, 2006 memory will always result in bank 0 being accessed ir - respective of the value of bp. indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] accesses the ram pointed to by mp0 (01h) and mp1(03h) respectively. reading lo - cation 00h or 02h indirectly returns the result 00h. while, writing it indirectly leads to no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers used to access the ram by combining corresponding indirect addressing registers. accumulator acc the accumulator is closely related to alu operations. it is also mapped to location 05h of the ram and capable of operating with immediate data. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operations. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register status the status register (0ah) is 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pdf), and a watchdog time-out flag (to). it also records the status information and controls the operation sequence. ex - cept for the to and pdf flags, bits in the status register can be altered by instructions similar to other registers. data written into the status register does not alter the to or pdf flags. operations related to the status register, however, may yield different results from those in - tended. the to and pdf flags can only be changed by a watchdog timer overflow, chip power-up, or clearing the watchdog timer and executing the halt instruc - tion. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. interrupts the device provides an external interrupt, two internal timer/event counter interrupt, the a/d converter interrupt and the i 2 c bus interrupts. the interrupt control register 0 (intc0;0bh) and interrupt control register 1 (intc1;1eh) contains the interrupt control bits to set the enable/disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter - rupt requires servicing within the service routine, the bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register ht46r24/ht46c24 rev. 2.00 10 march 2, 2006 emi bit and the corresponding bit of intc0 and intc1 may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be pre - vented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro - gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con - tents should be saved in advance. external interrupts are triggered by a high to low transi - tion of int and the related interrupt request flag (eif; bit 4 of intc0) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter 0 interrupt is initial - ized by setting the timer/event counter 0 interrupt re - quest flag (t0f; bit 5 of intc0), which is normally caused by a timer overflow. after the interrupt is en- abled, and the stack is not full, and the t0f bit is set, a subroutine call to location 08h occurs. the related inter- rupt request flag (t0f) is reset, and the emi bit is cleared to disable further maskable interrupts. the timer/event counter 1 is operated in the same manner but its related interrupt request flag is t1f (bit 6 of intc0) and its subroutine call location is 0ch. the a/d converter interrupt is initialized by setting the a/d converter request flag (adf; bit 4 of intc1), caused by an end of a/d conversion. when the interrupt is enabled, the stack is not full and the adf is set, a sub - routine call to location 10h will occur. the related inter - rupt request flag (adf) will be reset and the emi bit cleared to disable further interrupts. the i 2 c bus interrupt is initialized by setting the i 2 c bus in - terrupt request flag ( hif; bit 5 of intc1), caused by a slave address match (h aas= 1 ) or one byte of data transfer is completed. when the interrupt is enabled, the stack is not full and the hif bit is set, a subroutine call to location 14h will occur. the related interrupt request flag (hif) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to en - able an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter- rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei controls the external interrupt (1= enabled; 0= disabled) 2 et0i controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) 3 et1i controls the timer/event counter 1 interrupt (1= enabled; 0= disabled) 4 eif external interrupt request flag (1= active; 0= inactive) 5 t0f internal timer/event counter 0 request flag (1= active; 0= inactive) 6 t1f internal timer/event counter 1 request flag (1= active; 0= inactive) 7 for test mode used only. must be written as 0 ; otherwise may result in unpredictable operation. intc0 (0bh) register bit no. label function 0 eadi control the a/d converter interrupt (1= enabled; 0=disabled) 1 ehi control the i 2 c bus interrupt (1= enabled; 0= disabled) 2, 3 unused bit, read as 0 4 adf a/d converter request flag (1= active; 0= inactive) 5 hif i 2 c bus interrupt request flag (1= active; 0= inactive) 6, 7 unused bit, read as 0 intc1(1eh) register ht46r24/ht46c24 rev. 2.00 11 march 2, 2006 interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch a/d converter interrupt 4 10h i 2 c bus interrupt 5 14h the timer/event counter 0/1 interrupt request flag (t0f, t1f), external interrupt request flag (eif), a/d converter request flag (adf), the i 2 c bus interrupt request flag (hif), enable timer/event counter bit (et0i, et1i), en - able external interrupt bit (eei), enable a/d converter in - terrupt bit (eadi), enable i 2 c bus interrupt bit (ehi) and enable master interrupt bit (emi) constitute an interrupt control register 0 (intc0) and an interrupt control regis - ter 1 (intc1) which are located at 0bh and 1eh in the data memory. emi, eei, et0i, et1i, eadi, ehi are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags (t0f, t1f, eif, adf, hif) are set, they will remain in the intc0 and intc1 register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. inter - rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con- trolled, the original control sequence will be damaged once the call operates in the interrupt subroutine. oscillator configuration there are two oscillator circuits in the microcontroller. both are designed for system clocks, namely the rc os - cillator and the crystal oscillator, which are determined by the option. no matter what oscillator type is selected, the signal provides the system clock. the halt mode stops the system oscillator and ignores an external sig - nal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vss is required and the resistance must range from 30k to 750k . the system clock, divided by 4, is available on osc2 with pull-high resistor, which can be used to synchronize external logic. the rc os - cillator provides the most cost effective solution. how - ever, the frequency of oscillation may vary with vdd, temperatures and the chip itself due to process varia - tions. it is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. instead of a crystal, a resona - tor can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required (if the oscillating fre - quency is less than 1mhz). the wdt oscillator is a free running on-chip rc oscillator, and no external components are required. even if the sys - tem enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approximately 65 s at 5v. the wdt oscillator can be dis - abled by option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys - tem clock divided by 4) decided by options. this timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable re - sults. the watchdog timer can be disabled by a option. if the watchdog timer is disabled, all the executions re- lated to the wdt result in no operation. once an internal wdt oscillator (rc oscillator with pe- riod 65 s at 5v normally) is selected, it is divided by 2 12 ~2 15 (by option to get the wdt time-out period). the wdt time-out minimum period is 300ms~600ms. this time-out period may vary with temperature, vdd and process variations. by selection from the wdt option, longer time-out periods can be realized. if the wdt time-out is selected 2 15 , the maximum time-out period is divided by 2 15 ~2 16 about 2.1s~4.3s. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. the wdt overflow under normal operation will initialize chip reset and set the status bit to. whereas in the halt mode, the overflow will initialize a warm reset only the program counter and stack pointer are reset to zero. to clear the contents of wdt, three methods are adopted; external reset (a low level to res ), software in - structions, or a halt instruction. the software instruc - tions include clr wdt and the other set clr wdt1 and clr wdt2. of these two types of instruction, only one can be active depending on the option clr wdt times selection option .ifthe clr wdt is selected (i.e. . ) . . ) . . $ , ' - - 1 + * system oscillator ht46r24/ht46c24 rev. 2.00 12 march 2, 2006 clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case clr wdt1 and clr wdt2 are chosen (i.e. clrwdt times equal two), these two instructions must be exe - cuted to clear the wdt; otherwise, the wdt may reset the chip because of time-out. if the wdt time-out period is selected f s /2 12 (option), the wdt time-out period ranges from f s /2 12 ~f s /2 13 , since the clr wdt or clr wdt1 and clr wdt2 instructions only clear the last two stages of the wdt. power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator turned off but the wdt oscillator keeps running (if the wdt oscillator or the real time clock is selected). the contents of the on-chip ram and registers remain unchanged the wdt will be cleared and start recounting (if the wdt clock source is from the wdt oscillator or the real time clock) all of the i/o ports maintain their original status the pdf flag is set and the to flag is cleared the system quits the halt mode by an external reset, an interrupt, an external falling edge signal on port a or a wdt overflow. an external reset causes a device initial - ization and the wdt overflow performs a warm reset . after examining the to and pdf flags, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or by executing the clr wdt in - struction and is set when executing the halt instruc - tion. on the other hand, the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp; and leaves the others in their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by the option. awakening from an i/o port stimu - lus, the program will resume execution of the next in - struction. if it is awakening from an interrupt, two sequences may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the pro - gram will resume execution at the next instruction. but if the interrupt is enabled and the stack is not full, the regu - lar interrupt response takes place. when an interrupt re - quest flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be dis - abled. if wake-up event occurs, it takes 1024 f sys (sys - tem clock period) to resume normal operation. in other words, a dummy period is inserted after wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. however, if the wake-up results in the next instruction execution, this will be executed per - formed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset may occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and sp, leaves the other circuits at their original state. some registers re - main unaffected during any other reset conditions. most registers are reset to the initial condition when the re - set conditions are met. examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem awakes from the halt state or during power up. awaking from the halt state or system power up an sst delay is added. an extra sst delay is added during $ ' 3 ) . = ' - 5 ! ( ) . = ) = . ( $ ( ) . 4 ) ) ) ' $ ) / ) ) ) ' $ ) ) ' $ ) / ) ) ) ' $ ) ) ) ' $ ) / ) ) ) ' $ ) ) ) ' $ ) / ) ) ) ' $ ) 6 7 - 6 0 - 0 watchdog timer ht46r24/ht46c24 rev. 2.00 13 march 2, 2006 power up period, and any wake-up from halt may en - able only the sst delay. the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler, divider cleared wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack timer/event counter two timer/event counters (tmr0,tmr1) are imple - mented in the microcontroller. the timer/event counter 0 contains an 16-bit programmable count-up counter and the clock may come from an external source or an inter - nal clock source. an internal clock source comes from f sys . the timer/event counter 1 contains an 16-bit pro - grammable count-up counter and the clock may come from an external source or an internal clock source. an internal clock source comes from f sys /4. the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. there are six registers related to the timer/event coun - ter 0; tmr0h (0ch), tmr0l (0dh), tmr0c (0eh) and the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). writing tmr0l (tmr1l) will only put the written data to an internal lower-order byte buffer (8-bit) and writing tmr0h (tmr1h) will transfer the specified data and the contents of the lower-order byte buffer to tmr0h (tmr1h) and tmr0l (tmr1l) regis - ters, respectively. the timer/event counter 1/0 preload register is changed by each writing tmr0h (tmr1h) operations. reading tmr0h (tmr1h) will latch the contents of tmr0h (tmr1h) and tmr0l (tmr1l) counters to the destination and the lower-order byte buffer, respectively. reading the tmr0l (tmr1l) will read the contents of the lower-order byte buffer. the tmr0c (tmr1c) is the timer/event counter 0 (1) con - trol register, which defines the operating mode, counting enable or disable and an active edge. the t0m0, t0m1 (tmr0c) and t1m0, t1m1 (tmr1c) bits define the operation mode. the event count mode is used to count external events, which means that the clock source is from an external (tmr0, tmr1) pin. the timer mode functions as a normal timer with the clock source coming from the internal selected clock source. finally, the pulse width measurement mode can be used to count the high or low level duration of the external sig- nal (tmr0, tmr1), and the counting is based on the in- ternal selected clock source. in the event count or timer mode, the timer/event coun- ter starts counting at the current contents in the timer/event counter and ends at ffffh. once an over - flow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt re - quest flag (t0f; bit 5 of intc0, t1f; bit 6 of intc0). in the pulse width measurement mode with the values of the t0on/t1on and t0e/t1e bits equal to 1, after the tmr0 (tmr1) has received a transient from low to high (or high to low if the t0e/t1e bit is 0 ), it will start count - ing until the tmr0 (tmr1) returns to the original level and resets the t0on/t1on. the measured result re - mains in the timer/event counter even if the activated transient occurs again. in other words, only 1-cycle measurement can be made until the t0on/t1on is set. the cycle measurement will re-function as long as it re - ceives further transient pulse. in this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt re - quest, as in the other two modes, i.e., event and timer modes. ( ) ( & " . ! @ 4 ) + 4 ? ) . ( ; . 4 reset configuration < ) 4 # ) ) reset timing chart + + = + = + d * e + d + * e reset circuit note: * make the length of the wiring, which is con - nected to the res pin as short as possible, to avoid noise interference. ht46r24/ht46c24 rev. 2.00 14 march 2, 2006 the registers states are summarized in the following table. register reset(power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* tmr0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- program counter 000h 000h 000h 000h 000h mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pf 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pwm0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu hadr xxxx xxx- xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu- hcr 0--0 0--- 0--0 0--- 0--0 0--- 0--0 0--- u--u u--- hsr 100- -0-1 100- -0-1 100- -0-1 100- -0-1 uuuu uuuu hdr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrl xx-- ---- xx-- ---- xx-- ---- xx-- ---- uu-- ---- adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu acsr 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu note: * stands for warm reset u stands for unchanged x stands for unknown ht46r24/ht46c24 rev. 2.00 15 march 2, 2006 to enable the counting operation, the timer on bit (t0on: bit 4 of tmr0c; t10n: bit 4 of tmr1c) should be set to 1. in the pulse width measurement mode, the t0on/t1on is automatically cleared after the measure - ment cycle is completed. but in the other two modes, the t0on/t1on can only be reset by instructions. the overflow of the timer/event counter 0/1 is one of the wake-up sources and can also be applied to a pfd (pro - grammable frequency divider) output at pa3 by op - tions. only one pfd (pfd0 or pfd1) can be applied to pa3 by options. if pa3 is set as pfd output, there are two types of selections; one is pfd0 as the pfd output, the other is pfd1 as the pfd output. pfd0, pfd1 are the timer overflow signals of the timer/event counter 0, timer/event counter 1 respectively. no matter what the operation mode is, writin ga0to et0i or et1i disables the related interrupt service. when the pfd function is selected, executing set [pa].3 instruction to enable pfd output and executing clr [pa].3 instruction to disable pfd output. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also re - loads that data to the timer/event counter. but if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event coun - ter preload register. the timer/event counter still contin - ues its operation until an overflow occurs. when the timer/event counter (reading tmr0/tmr1) is read, the clock is blocked to avoid errors, as this may re - sults in a counting error. blocking of the clock should be taken into account by the programmer. it is strongly rec - ommended to load a desired value into the tmr0/tmr1 register first, before turning on the related timer/event counter, for proper operation since the initial value of tmr0/tmr1 is unknown. due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. after this procedure, the timer/event function can be operated normally. + + + + + + + + + . ) ( ! # ! ) . 3 4 ) . 3 4 ) $ , $ + / + + 9 7 < : ) ) 9 1 < : ( ) + ' ' ' 0 ) 7 4 2 . ! ) ) 2 . ! 5 $ . @ ) ) " @ ) 2 2 $ $ & # ) 2 " @ ) 2 7 4 2 ) ' 5 ) * + timer/event counter 0 + + . ) ( ! # ! ) . $ , ' - $ 7 4 2 . ! ) ) 2 . ! 5 $ . @ ) ) " @ ) 2 2 $ $ & # ) 2 " @ ) 2 7 4 2 ) ' 5 ) * timer/event counter 1 ' * * ) ) 0 ) ) " * + * pfd source option ht46r24/ht46c24 rev. 2.00 16 march 2, 2006 the bit0~bit2 of the tmr0c can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. the definitions are as shown. the overflow signal of timer/event counter can be used to generate the pfd sig - nal. the timer prescaler is also used as the pwm counter. bit no. label function 0 1 2 t0psc0 t0psc1 t0psc2 defines the prescaler stages, t0psc2, t0psc1, t0psc0= 000: f int =f sys 001: f int =f sys /2 010: f int =f sys /4 011: f int =f sys /8 100: f int =f sys /16 101: f int =f sys /32 110: f int =f sys /64 111: f int =f sys /128 3 t0e defines the tmr0 active edge of the timer/event counter: in event counter mode (t0m1,t0m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t0m1,t0m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t0on enable/disable timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 6 7 t0m0 t0m1 defines the operating mode, t0m1, t0m0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh) register bit no. label function 0~2 unused bit, read as 0 3 t1e defines the tmr1 active edge of the timer/event counter: in event counter mode (t1m1,t1m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t1m1,t1m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t1on enable/disable timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 6 7 t1m0 t1m1 defines the operating mode, t1m1, t1m0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr1c (11h) register ht46r24/ht46c24 rev. 2.00 17 march 2, 2006 input/output ports there are 40 bidirectional input/output lines in the microcontroller, labeled as pa, pb, pc, pd and pf, which are mapped to the data memory of [12h], [14h], [16h], [18h] and [28h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the in - puts must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h, [18h] or 28h). for out - put operation, all the data is latched and remains un - changed until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc, pfc) to control the input/output configura - tion. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. to function as an input, the corresponding latch of the control register must write 1 . the input source also de - pends on the control register. if the control register bit is 1 , the input will read the pad state. if the control regis - ter bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify- write instruction. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h, 17h, 19h and 29h. after a chip reset, these input/output lines remain at high levels or floating state (depends on pull-high options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h, 16h 18h or 28h) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. each i/o port has a pull-high option. once the pull-high option is selected, the i/o port has a pull-high resistor, otherwise, there s none. take note that a non-pull-high i/o port operating in input mode will cause a floating state. the pa3 and pa5 are pin-shared with the pfd and int pins respectively. if the pfd option is selected, the out - put signal in output mode of pa3 will be the pfd signal generated by timer/event counter overflow signal. the input mode always remain in its original functions. once the pfd option is selected, the pfd output signal is con - trolled by pa3 data register only. writing 1 to pa3 data register will enable the pfd output function and writing 0 will force the pa3 to remain at 0 . the i/o functions of pa3 are shown below. i/o mode i/p (normal) o/p (normal) i/p (pfd) o/p (pfd) pa3 logical input logical output logical input pfd (timer on) note: the pfd frequency is the timer/event counter overflow frequency divided by 2. the pb can also be used as a/d converter inputs. the a/d function will be described later. there is a pwm function shared with pd0/pd1/pd2/pd3. if the pwm function is enabled, the pwm0/pwm1/pwm2/pwm3 signal will appear on pd0/pd1/pd2/pd3 (if pd0/pd1/ pd2/pd3 is operating in output mode). the i/o func- tions of pd0/pd1/pd2/pd3 are as shown. 9 * ) ( + / ( 0 : + / 1 ) $ ) 6 ) . ) ( = 4 9 ) . : ! ) ) f f f . ) 2 ) 2 ( ) . ) # ) ! ) . ) ( ) ) ) 2 + / 0 ' * - 6 ' 7 ' 1 ' " 2 + ' + / 2 1 ' 1 + / 1 + ' ( + ' ( ' ( 0 ' ( 0 - / 1 * + / * 1 f ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) g 0 c ) * h ) ) ) ) g + c ( + h ) g c ( h ) g c ( h ) g 0 c ( 0 h input/output ports ht46r24/ht46c24 rev. 2.00 18 march 2, 2006 i/o mode i/p (normal) o/p (normal) i/p (pwm) o/p (pwm) pd0 pd1 pd2 pd3 logical input logical output logical input pwm0 pwm1 pwm2 pwm3 it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. pwm the microcontroller provides 4 channels (6+2)/(7+1) (depends on options) bits pwm output shared with pd0/pd1/pd2/pd3. the pwm channels have their data registers denoted as pwm0 (1ah), pwm1 (1bh), pwm2 (1ch) and pwm3 (1dh). the frequency source of the pwm counter comes from f sys . the pwm regis - ters are four 8-bit registers. the waveforms of pwm outputs are as shown. once the pd0/pd1/pd2/pd3 are selected as the pwm outputs and the output function of pd0/pd1/pd2/pd3 are enabled (pdc.0/pdc.1/ pdc.2/pdc.3 = 0 ), writing 1 to pd0/pd1/pd2/pd3 data register will enable the pwm output function and writing 0 will force the pd0/pd1/pd2/pd3 to stay at 0 . a (6+2) bits mode pwm cycle is divided into four modu - lation cycles (modulation cycle 0~modulation cycle 3). each modulation cycle has 64 pwm input clock period. in a (6+2) bit pwm function, the contents of the pwm register is divided into two groups. group 1 of the pwm register is denoted by dc which is the value of pwm.7~pwm.2. the group 2 is denoted by ac which is the value of pwm.1~pwm.0. $ , ' ( g ( h ) i + + g ( h ) i + ( g ( h ) i + ( g ( h ) i + 0 ( ( ) . ) a ) 6 7 ' $ , 6 ' 7 - 7 ' 7 - 7 ' 7 - 7 ' 7 - 6 ' 7 - 6 ' 7 - 6 ' 7 - 6 ' 7 - 6 ' 7 - 6 ' 7 - 6 ' 7 - 7 ' 7 - 7 ' 7 - 6 ' 7 - 6 ' 7 - 7 ' 7 - 6 ' 7 - 7 ' 7 - 7 ' 7 - 7 ' 7 - ! . ) . ) + ( ) ! . ) ! ) a ) 7 - ' $ , ! . ) . ) ! . ) . ) ! . ) . ) 0 ! . ) . ) + (6+2) pwm mode $ , ' ( g ( h ) i + + g ( h ) i + ( g ( h ) i + ( g ( h ) i + 0 ( ( ) ! . ) ! ) a ) 3 ' $ , 6 + ' 3 6 ' 3 6 ' 3 6 ' 3 6 + ' 3 6 + ' 3 6 ' 3 6 ' 3 6 + ' 3 6 ' 3 6 ' 3 6 ' 3 ! . ) . ) + ( ) . ) a ) 6 7 ' $ , ! . ) . ) ! . ) . ) + (7+1) pwm mode ht46r24/ht46c24 rev. 2.00 19 march 2, 2006 in a (6+2) bits mode pwm cycle, the duty cycle of each modulation cycle is shown in the table. parameter ac (0~3) duty cycle modulation cycle i (i=0~3) i ht46r24/ht46c24 rev. 2.00 21 march 2, 2006 the following two programming examples illustrate how to setup and implement an a/d conversion. in the first exam - ple, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using eocb polling method to detect end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock mov a,00100000b ; setup adcr register to configure port pb0~pb3 as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : : ; as the port b channel bits have changed the following start ; signal (0-1-0) must be issued within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adrh ; read conversion result high byte value from the adrh register mov adrh_buffer,a ; save result to user defined memory mov a,adrl ; read conversion result low byte value from the adrl register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next a/d conversion example: using interrupt method to detect end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock mov a,00100000b ; setup adcr register to configure port pb0~pb3 as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : ; as the port b channel bits have changed the following start ; signal (0-1-0) must be issued within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request flag set eadi ; enable adc interrupt set emi ; enable global interrupt : : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defined memory mov a,status ht46r24/ht46c24 rev. 2.00 22 march 2, 2006 mov status_stack,a ; save status to user defined memory : : mov a,adrh ; read conversion result high byte value from the adrh register mov adrh_buffer,a ; save result to user defined register mov a,adrl ; read conversion result low byte value from the adrl register mov adrl_buffer,a ; save result to user defined register clr start set start ; reset a/d clr start ; start a/d : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory reti ' ) 5 ) ' ) 5 ) ' ) 5 ) + + + 2 + + + 2 + + 2 + + 2 2 / + / + @ 4 ! ) $ ) ' 5 a ) $ ) 2 ) $ a ) . ) . ) # . ' ) . = ) ) ? ) $ , ' c ) $ , ' 3 ) ) $ , ' 0 i 0 i 1 7 a ) ) $ ) ' 5 ) ' 5 ' ) . ) ) ) ) + + 2 + + + 2 ) $ ) ' 5 ) ' 5 + + + 2 d ) 2 ) ) ) ) ' d ) ' ) 5 ) ) @ ! ) $ $ ) ) ) ) ) ! ) @ ) + 2 + + 2 ) $ ) ' 5 ) ' 5 ! j ) ! ) $ ) ' 5 ! ) $ ) ' 5 ) ) ) . ) ! ! c ) ; ) ) ) . ) . . @ ! ' ) . ) ) ) ) ' ) . ) ) ) ) a/d conversion timing ht46r24/ht46c24 rev. 2.00 23 march 2, 2006 low voltage reset lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as changing a battery, the lvr will au - tomatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in their original state to exceed 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip operation at 4mhz system clock. 6 d 6 0 d + d + d 8 " 6 d 6 6 d 6 " + d 8 + ) . e e . ) " ) ) . low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. ht46r24/ht46c24 rev. 2.00 24 march 2, 2006 i 2 c bus serial interface i 2 c bus is implemented in the device. the i 2 c bus is a bidirectional two-wire lines. the data line and clock line are implement in sda pin and scl pin. the sda and scl are nmos open drain output pin. they must con - nect a pull-high resistor respectively. using the i 2 c bus, the device has two ways to transfer data. one is in slave transmit mode, the other is in slave receive mode. there are four registers related to i 2 c bus; hadr([20h]), hcr([21h]), hsr([22h]), hdr([23h]). the hadr register is the slave address setting of the device, if the master sends the calling ad - dress which match, it means that this device is selected. the hcr is i 2 c bus control register which defines the device enable or disable the i 2 c bus as a transmitter or as a receiver. the hsr is i 2 c bus status register, it re - sponds with the i 2 c bus status. the hdr is input/output data register, data to transmit or receive must be via the hdr register. the i 2 c bus control register contains three bits. the hen bit defines whether to enable or disable the i 2 c bus. if the data wants to transfer via i 2 c bus, this bit must be set. the htx bit defines whether the i 2 c bus is in transmit or receive mode. if the device is as a trans - mitter, this bit must be set to 1 . the txak defines the transmit acknowledge signal, when the device received 8-bit data, the device sends this bit to i 2 c bus at the 9th clock. if the receiver wants to continue to receive the next data, this bit must be reset to 0 before receiving data. the i 2 c bus status register contains 5 bits. the hcf bit is reset to 0 when one data byte is being transferred. if one data transfer is completed, this bit is set to 1 . the haas bit is set 1 when the address is match, and the i 2 c bus interrupt request flag is set to 1 . if the interrupt is enabled and the stack is not full, a subroutine call to location 10h will occur. writing data to the i 2 c bus con - trol register clears haas bit. if the address is not match, this bit is reset to 0 . the hbb bit is set to respond the i 2 c bus is busy. it mean that a start signal is detected. this bit is reset to 0 when the i 2 c bus is not busy. it means that a stop signal is detected and the i 2 c bus is free. the srw bit defines the read/write command bit, if the calling address is match. when haas is set to 1 , the device check srw bit to determine whether the de - vice is working in transmit or receive mode. when srw bit is set 1 , it means that the master wants to read data from i 2 c bus, the slave device must write data to i 2 c bus, so the slave device is working in transmit mode. when srw is reset to 0 , it means that the master wants to write data to i 2 c bus, the slave device must read data from the bus, so the slave device is working in receive mode. the rxak bit is reset 0 indicates an ac - knowledges signal has been received. in the transmit mode, the transmitter checks rxak bit to know the re - ceiver which wants to receive the next data byte, so the transmitter continue to write data to the i 2 c bus until the rxak bit is set to 1 and the transmitter releases the sda line, so that the master can send the stop signal to release the bus. the hadr bit7-bit1 define the device slave address. at the beginning of transfer, the master must select a de - vice by sending the address of the slave device. the bit 0 is unused and is not defined. if the i 2 c bus receives a start signal, all slave device notice the continuity of the 8-bit data. the front of 7 bits is slave address and the first bit is msb. if the address is match, the haas status bit is set and generate an i 2 c bus interrupt. in the isr, the slave device must check the haas bit to know the i 2 c bus interrupt comes from the slave address that has match or completed one 8-bit data transfer. the last bit of the 8-bit data is read/write command bit, it responds in srw bit. the slave will check the srw bit to know if the master wants to transmit or receive data. the device check srw bit to know it is as a transmitter or receiver. bit7~bit1 bit0 slave address note: means undefined hadr (20h) register the hdr register is the i 2 c bus input/output data regis - ter. before transmitting data, the hdr must write the data which needs to be transmitted. before receiving data, the device must dummy read data from hdr. transmit or receive data from i 2 c bus must be via the hdr register. ht46r24/ht46c24 rev. 2.00 25 march 2, 2006 at the beginning of the transfer of the i 2 c bus, the device must initial the bus, the following are the notes for initialing the i 2 c bus: note: 1: write the i 2 c bus address register (hadr) to define its own slave address. 2: set hen bit of i 2 c bus control register (hcr) bit 0 to enable the i 2 c bus. bit no. label function 0~2 unused bit, read as 0 3 txak enable/disable transmit acknowledge (0=acknowledge; 1=don t acknowledge) 4 htx defines the transmit/receive mode (0=receive mode; 1=transmit) 5~6 unused bit, read as 0 7 hen enable/disable i 2 c bus function (0=disable; 1=enable) hcr (21h) register 3: set ehi bit of the interrupt control register 1 (intc1) bit 0 to enable the i 2 c bus interrupt. bit no. label function 0 rxak rxak is cleared to 0 when the master receives an 8-bit data and acknowledgment at the 9th clock, rxak is set to 1 means not acknowledged. 1 unused bit, read as 0 2 srw srw is set to 1 when the master wants to read data from the i 2 c bus, so the slave must transmit data to the master. srw is cleared to 0 when the master wants to write data to the i 2 c bus, so the slave must receive data from the master. 3~4 unused bit, read as 0 5 hbb hbb is set to 1 when i 2 c bus is busy and hbb is cleared to 0 means that the i 2 c bus is not busy. 6 haas haas is set to 1 when the calling address has matched, and i 2 c bus interrupt will occur and hcf is set. 7 hcf hcf is cleared to 0 when one data byte is being transferred, hcf is set to 1 indicating 8-bit data communication has been finished. hsr (22h) register ht46r24/ht46c24 rev. 2.00 26 march 2, 2006 & i k & i ) ) ) ) k ( i ) ) ) ) ) k , , i k , ! ) $ ) & , ) ! $ ) & ( ) ) & ) & ( ) ) & ) ! * ) & " ) & " ) " ) & " ) ) ) ( ) . 5 ) ) ! ! ) ) & ) & ) ) ) ) 2 i k ) ? . ? . ) ) ) ) & ( ) $ ) % ) ) " ) & ) . . ) & * ) ) ! ! ) @ # ) ) ) ) ) 2 ) ) % ) ) ht46r24/ht46c24 rev. 2.00 27 march 2, 2006 + ) ) ) ) ) ) ) + + ) ) ) ) ) ) ) + + + + + + i ) 9 ) ? : i . 5 ) ! ! ) 9 1 ) ? : i ( ) ? ) 9 ) ? : i . 5 ) ! 5 ) ! ) = @ . ! ) ? ) 9 ) ? : i ) 9 3 ) ? : i ) 9 ) ? ) $ ) c ) ) ? ) $ ) 5 ) ) ? : i ) 9 ) ? : " ( " . 5 ) ! ! i 2 c communication timing diagram start signal the start signal is generated only by the master de- vice. the other device in the bus must detect the start signal to set the i 2 c bus busy bit (hbb). the start sig- nal is sda line from high to low, when scl is high. slave address the master must select a device for transferring the data by sending the slave device address after the start signal. all device in the i 2 c bus will receive the i 2 c bus slave address (7 bits) to compare with its own slave address (7 bits). if the slave address is matched, the slave device will generate an interrupt and save the following bit (8th bit) to srw bit and sends an acknowl - edge bit (low level) to the 9th bit. the slave device also sets the status flag (haas), when the slave address is matched. in interrupt subroutine, check haas bit to know whether the i 2 c bus interrupt comes from a slave address that is matched or a data byte transfer is completed. when the slave address is matched, the device must be in trans - mit mode or receive mode and write data to hdr or dummy read from hdr to release the scl line. srw bit the srw bit means that the master device wants to read from or write to the i 2 c bus. the slave device check this bit to understand itself if it is a transmitter or a receiver. the srw bit is set to 1 means that the mas- ter wants to read data from the i 2 c bus, so the slave de- vice must write data to a bus as a transmitter. the srw is cleared to 0 means that the master wants to write data to the i 2 c bus, so the slave device must read data from the i 2 c bus as a receiver. acknowledge bit one of the slave device generates an acknowledge signal, when the slave address is matched. the master device can check this acknowledge bit to know if the slave device accepts the calling address. if no acknowledge bit, the master must send a stop bit and end the communication. when the i 2 c bus status register bit 6 haas is high, it means the address is matched, so the slave must check srw as a transmitter (set htx) to 1 or as a receiver (clear htx) to 0 . " start bit " stop bit ht46r24/ht46c24 rev. 2.00 28 march 2, 2006 data byte the data is 8 bits and is sent after the slave device has acknowledged the slave address. the first bit is msb and the 8th bit is lsb. the receiver sends the acknowl - edge signal ( 0 ) and continues to receive the next one byte data. if the transmitter checks and there snoac - knowledge signal, then it release the sda line, and the master sends a stop signal to release the i 2 c bus. the data is stored in the hdr register. the transmitter must write data to the hdr before transmitting data and the receiver must read data from the hdr after receiving data. receive acknowledge bit when the receiver wants to continue to receive the next data byte, it generates an acknowledge bit (txak) at the 9th clock. the transmitter checks the acknowledge bit (rxak) to continue to write data to the i 2 c bus or change to receive mode and dummy read the hdr reg - ister to release the sda line and the master sends the stop signal. " ) ? ) ) ) ? . ) ) ) ) . . @ # ) ? data timing diagram options the following shows kinds of options in the device. all the options must be defined to ensure proper system function. options osc type selection. this option is to decide if an rc or crystal oscillator is chosen as system clock. wdt source selection. there are three types of selection: on-chip rc oscillator, instruction clock or disable the wdt. clrwdt times selection. this option defines how to clear the wdt by instruction. one time means that the clr wdt instruction can clear the wdt. two times means only if both of the clr wdt1 and clr wdt2 instructions have been executed, then wdt can be cleared. wake-up selection. this option defines the wake-up function activity. external i/o pins (pa only) all have the capability to wake-up the chip from a halt by a falling edge. (bit option) pull-high selection. this option is to decide whether a pull-high resistance is visible or not in the input mode of the i/o ports. pa and pb are bit option; pc, pd and pf are port option. pfd selection. if pa3 is set as pfd output, there are two types of selections; one is pfd0 as the pfd output, the other is pfd1 as the pfd output. pfd0, pfd1 are the timer overflow signals of the timer/event counter 0, timer/event counter 1 re - spectively. pwm selection: (7+1) or (6+2) mode pd0: level output or pwm0 output pd1: level output or pwm1 output pd2: level output or pwm2 output pd3: level output or pwm3 output wdt time-out period selection. 2 12 /f s ~2 13 /f s ,2 13 /f s ~2 14 /f s ,2 14 /f s ~2 15 /f s ,2 15 /f s ~2 16 /f s . i 2 c bus function: enable or disable lvr selection. lvr has enable or disable options application circuits the following table shows the c1, c2 and r1 values corresponding to the different crystal values. (for reference only) crystal or resonator c1, c2 r1 4mhz crystal 0pf 10k 4mhz resonator 10pf 12k 3.58mhz crystal 0pf 10k 3.58mhz resonator 25pf 10k 2mhz crystal & resonator 25pf 10k 1mhz crystal 35pf 27k 480khz resonator 300pf 9.1k 455khz resonator 300pf 10k 429khz resonator 300pf 10k the function of the resistor r1 is to ensure that the oscillator will switch off should low voltage condi - tions occur. such a low voltage, as mentioned here, is one which is less than the lowest value of the mcu operating voltage. note however that if the lvr is enabled then r1 can be removed. note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high. * make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference. ht46r24/ht46c24 rev. 2.00 29 march 2, 2006 + d * e + + = + d * + d + * e + = 0 + = l l 1 6 + = $ , ' - - 1 + * * ) # ) 5 . c ) ? . ) ? . @ / 2 + ' + 2 1 ' 1 + / 0 ' * - 6 ' 7 ' 1 ' " + / 1 - / 1 * + / * 1 ! / + ' ( + 0 ' ( 0 + instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none ht46r24/ht46c24 rev. 2.00 30 march 2, 2006 mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. ht46r24/ht46c24 rev. 2.00 31 march 2, 2006 instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) to pdf ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) to pdf ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) to pdf ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) to pdf ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 32 march 2, 2006 and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) to pdf ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) to pdf ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) to pdf ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack program counter+1 program counter addr affected flag(s) to pdf ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 33 march 2, 2006 clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) to pdf ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt 00h pdf and to 0 affected flag(s) to pdf ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im- plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 34 march 2, 2006 cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) to pdf ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) to pdf ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 35 march 2, 2006 halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation program counter program counter+1 pdf 1 to 0 affected flag(s) to pdf ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) to pdf ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) to pdf ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation program counter addr affected flag(s) to pdf ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 36 march 2, 2006 mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) to pdf ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) to pdf ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation program counter program counter+1 affected flag(s) to pdf ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) to pdf ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) to pdf ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 37 march 2, 2006 ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation program counter stack affected flag(s) to pdf ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation program counter stack acc x affected flag(s) to pdf ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation program counter stack emi 1 affected flag(s) to pdf ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) to pdf ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 38 march 2, 2006 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) to pdf ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) to pdf ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) to pdf ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) to pdf ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 39 march 2, 2006 rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) to pdf ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) to pdf ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) to pdf ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) to pdf ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 40 march 2, 2006 set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) to pdf ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) to pdf ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) to pdf ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) to pdf ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 41 march 2, 2006 sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) to pdf ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) to pdf ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) to pdf ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) to pdf ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 42 march 2, 2006 sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 43 march 2, 2006 xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) to pdf ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) to pdf ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) to pdf ov z ac c ht46r24/ht46c24 rev. 2.00 44 march 2, 2006 package information 28-pin skdip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 1375 1395 b 278 298 c 125 135 d 125 145 e16 20 f50 70 g 100 h 295 315 i 330 375 0 15 ht46r24/ht46c24 rev. 2.00 45 march 2, 2006 ) ) 3 6 - 2 * % & 28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12 0 10 ht46r24/ht46c24 rev. 2.00 46 march 2, 2006 3 6 - 2 * j % & 48-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 613 637 d85 99 e 25 f4 10 g25 35 h4 12 0 8 ht46r24/ht46c24 rev. 2.00 47 march 2, 2006 - 3 6 - 2 * j % & product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 62 1.5 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 ssop 48w symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 100 0.1 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 32.2+0.3 0.2 t2 reel thickness 38.2 0.2 ht46r24/ht46c24 rev. 2.00 48 march 2, 2006 2 carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.1 b0 cavity width 18.34 0.1 k0 cavity depth 2.97 0.1 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 ht46r24/ht46c24 rev. 2.00 49 march 2, 2006 ( + * + 2 + + ssop 48w symbol description dimensions in mm w carrier tape width 32.0 0.3 p cavity pitch 16.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 14.2 0.1 d perforation diameter 2.0 min. d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 12.0 0.1 b0 cavity width 16.20 0.1 k1 cavity depth 2.4 0.1 k2 cavity depth 3.2 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 25.5 ht46r24/ht46c24 rev. 2.00 50 march 2, 2006 + * 2 + + ( ht46r24/ht46c24 rev. 2.00 51 march 2, 2006 copyright 2006 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 0755-8616-9908, 8616-9308 fax: 0755-8616-9533 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 028-6653-6590 fax: 028-6653-6591 holmate semiconductor, inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com |
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